My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
The Great Debate of AI Architecture | Engineering.com
8-Bit Precision for Training Deep Learning Systems | IBM Research Blog
Processing AI at the Edge: GPU, VPU, FPGA, ASIC Explained - ADLINK Blog
Review of ASIC accelerators for deep neural network - ScienceDirect
Google AI Blog: Chip Design with Deep Reinforcement Learning
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to Develop High-Performance Deep Neural Network Object Detection/Recognition Applications for FPGA-based Edge Devices - Embedded Computing Design
FPGA Based Deep Learning Accelerators Take on ASICs
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
Are ASIC Chips The Future of AI?
Analog architectures for neural network acceleration based on non-volatile memory: Applied Physics Reviews: Vol 7, No 3
Intel Speeds AI Development, Deployment and Performance with New Class of AI Hardware from Cloud to Edge | Business Wire
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
FPGA Based Deep Learning Accelerators Take on ASICs
FPGA vs GPU for Machine Learning Applications: Which one is better? - Blog - Company - Aldec
FPGA Based Deep Learning Accelerators Take on ASICs
How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices - Blog - Company - Aldec
FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review
Review of ASIC accelerators for deep neural network - ScienceDirect
ASIC Design Services | Microsemi
